In wireless communication equipments, tuners, and so forth, a frequency synthesizer using a PLL (also referred to as a PLL synthesizer, or simply a PLL) is widely used. FIG. 1 is a diagram showing one example of a typical configuration of a frequency synthesizer. Referring to FIG. 1, the frequency synthesize includes a VCO (Voltage Controlled Oscillator) group 5, a frequency divider circuit (variable frequency divider circuit) 4 that frequency-divides a VCO output 24 (frequency Fvco), a phase comparator 2 that detects a phase difference between a signal (frequency Fsig) 22 obtained by frequency division by the frequency divider circuit 4 and a signal (reference frequency Fref) 21 from a reference oscillator circuit 1, a loop filter (low pass filter LPF) 3 that smoothes an output signal from the phase comparator 2 and outputs a control voltage to the VCO group 5, and a VCO automatic control block 6 that selects one VCO from among the VCO group 5 and performs selection of a capacitor bank in the VCO concerned.
Each VCO of the VCO group 5 comprises a capacitor bank including a plurality of capacitance elements 56 to 58 for coarse frequency adjustment, an inductor 51, a varactor (varactor diode: variable capacitance element) 52 for fine adjustment of frequency, and a negative resistance unit 50. The negative resistance unit 50 compensates loss in an LC resonant circuit to enable the VCO to oscillate.
An output voltage 23 (Vtune: varactor control voltage) of a loop filter 3 is applied to a varactor 52 of the VCO group 5.
Selection of the capacitor bank in the VCO group 5 is performed by ON-OFF control of switches between the capacitor elements 56 to 58 and GND (ground) by a capacitor bank switching signal bit=0 to bit=N, from the VCO automatic control block 6.
With reference to FIG. 2, operation of this frequency synthesizer is described. FIG. 2 shows an external data signal, operations (VCO selection and capacitor bank selection) of the VCO automatic control block 6 of FIG. 1, and a PLL loop voltage (23 in FIG. 1).
In a case where a channel is changed, with the frequency synthesizer in a locked state, transfer of data such as channel setting information and the like is performed (data transfer period 1 in FIG. 2).
Next, the coarse frequency adjustment is performed, and the selection of the VCO, and the selection of the capacitor bank is performed (coarse frequency adjustment period 2).
Next, phase pull-in (loop pull-in) operation, changing the varactor control voltage (Vtune) 23 for fine frequency adjustment, is performed (fine frequency period 3 in FIG. 2).
Above, the time required for a series of frequency tuning, as shown in FIG. 2, is the total amount necessary for the channel setting data transfer, and the coarse frequency adjustment and the fine frequency adjustment (for example, from 1 ms (millisecond) to 3 ms).
However, together with temperature variation, the lock on the frequency synthesizer may be released. A detailed description will be given below concerning this.
As a capacitor bank switch, in general a MOSFET (Metal-Oxide-Semiconductor Field Effect transistor) is used. Even when the switch is in an OFF state, since MOSFET parasitic capacitance is present, an oscillation frequency changes in accordance with the change in temperature, due to the fact that the VCO varactor 52 and the parasitic capacitance of the capacitor bank switch each possess a temperature characteristic. Accordingly, the VCO varactor control voltage (Vtune) 23 changes so as to maintain a state in which the frequency is locked.
If this control voltage 23 exceeds a variable frequency range, the locked state can no longer be maintained. Thus, in the PLL, readjustment of the coarse frequency adjustment and fine frequency adjustment of the VCO is performed. That is, there is a possibility of data reception being frequently cut off due to the lock being released together with temperature variation. In order to solve this problem, it is desirable to suppress temperature dependency of the parasitic capacitance of the varactor and the capacitor bank due to the frequency temperature variation of a VCO main unit.
A circuit supplying a correction voltage equivalent to a temperature variation amount by a temperature compensation circuit is described in Patent Document 1 (JP Patent Kokai Publication No. JP-P2007-110504A) and Patent Document 2 (JP Patent Kokai Publication No. JP-P2006-135892A).
FIG. 3 is a diagram (FIG. 2 in Patent Document 1) showing a configuration of Patent Document 1 (JP Patent Kokai Publication No. JP-P2007-110504A). As shown in FIG. 3, a variable capacitance circuit 12a whose voltage can be controlled, an inductor circuit 11, a negative resistance circuit 13a, and a temperature variation monitor control circuit 20 that outputs a correction potential, are provided. The temperature variation monitor control circuit 20 adds a weighted potential equivalent to the temperature variation amount for a control potential, to be supplied to one end of variable capacitance elements V5 and V6.
FIG. 4 is a diagram (FIG. 1 in Patent Document 2) showing a configuration of Patent Document 2 (JP Patent Kokai Publication No. JP-P2006-135892A). A resonant circuit is provided with a negative resistor 19b, an inductor 19a, a first capacitor 18 in which capacitance changes according to a first voltage 17 given from outside, and a plurality of capacitors 11a, 11b, 11c, and 11d in which capacitance changes by a correction control voltage. The correction control voltage is generated by a logic synthesis (full adder 12) based on frequency information 13 and an automatic correction value 14. The automated correction value is corrected based on the frequency information, which is indicated from outside.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2007-110504A (FIG. 2)
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2006-135892A (FIG. 1)